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digital_design [ASIC Design Wiki:ESL RTL Verilog, System Modeling SystemC, Simulation, Synthesis ]
 

As a part of our digital design section we will be covering the following

  1. Representation of Boolean logic using Verilog or VHDL
  2. Clocks and resets, Here we cover Issues with Synchronous, Asynchronous resets, Multiclock designs, Glitch free clocks muxing, Synchronization techniques etc.
  3. Design of various basic structures such as circular buffers, FIFO's etc.
 
digital_design.txt · Last modified: 2010/04/06 10:10 by 59.92.152.40     Back to top