Warning: ob_start() [ref.outcontrol]: output handler 'ob_gzhandler' conflicts with 'zlib output compression' in /hermes/bosweb/web057/b571/nf.edaindia/public_html/wiki/inc/init.php on line 186
http://www.edaindia.com/wiki/ 2012-02-04T09:37:51-05:00 http://www.edaindia.com/wiki/ http://www.edaindia.com/wiki/lib/images/favicon.ico text/html 2011-11-01T13:40:06-05:00 ajay http://www.edaindia.com/wiki/esl?rev=1320169206&do=diff What is ESL? The term ESL is an abbreviation of Electronic System Level. Gartner Dataquest defines the term as “the utilization of appropriate abstractions in order to increase comprehension about a system, and to enhance the probability of a successful implementation of functionality in a cost-effective manner.” This indicates the following properties that an ESL methodology should have text/html 2011-11-01T13:39:14-05:00 ajay http://www.edaindia.com/wiki/low_power_asic_design?rev=1320169154&do=diff incomplete Low Power ASICS can be built using a mix of various techniques. These techniques are applicable at various design stages.img * Power Efficient Architecture * Clock Gating * Power Gating * Frequency Scaling * Voltage Scaling * Transistor threshold * Back Biasing * Reduce Oxide Thickness * FINFET * Power efficient circuits * Parallelism in micro-architecture text/html 2011-11-01T12:53:25-05:00 ajay http://www.edaindia.com/wiki/start?rev=1320166405&do=diff You are invited to contribute to this knowledgebase on design. Feel free to edit existing pages or add new ones on Aspects of IC Design be it ASIC FPGA or Systems This Wiki has been setup to consolidate the knowledge on System Architecture ASIC Design and Digital Design Techniques. We will be covering Traditional HDL's like Verilog, VHDL and ESL Tools based on C, C++, System Verilog We will cover different modeling strategies using SystemC, SpreadSheets, NS2, OmnetPP etc. And finally we wil…