http://www.edaindia.com/wiki/ 2012-05-20T00:25:28-04:00 http://www.edaindia.com/wiki/ http://www.edaindia.com/wiki//www.edaindia.com/wiki/lib/tpl/battlehorse/images/favicon.ico text/html 2009-12-16T11:10:56-04:00 http://www.edaindia.com/wiki/asic_design?rev=1260979856&do=diff incomplete The Asic design phase consists of the following steps * Requirement gathering * Requirement Analysis * Product Requirement document creation * System Specification * Hardware Software Partitioning * Hardware Requirement document creation * Hardware Architecture document creation * Hardware Micro-Architecture creation * Verification plan * Implementation plan * RTL coding * Testbench creation * Testcase creation. * Verification. * Synthesis. * DFT * … text/html 2010-04-06T10:10:17-04:00 http://www.edaindia.com/wiki/digital_design?rev=1270563017&do=diff As a part of our digital design section we will be covering the following * Representation of Boolean logic using Verilog or VHDL * Clocks and resets, Here we cover Issues with Synchronous, Asynchronous resets, Multiclock designs, Glitch free clocks muxing, Synchronization techniques etc. * Design of various basic structures such as circular buffers, FIFO's etc. text/html 2011-11-01T13:40:06-04:00 http://www.edaindia.com/wiki/esl?rev=1320169206&do=diff What is ESL? The term ESL is an abbreviation of Electronic System Level. Gartner Dataquest defines the term as “the utilization of appropriate abstractions in order to increase comprehension about a system, and to enhance the probability of a successful implementation of functionality in a cost-effective manner.” This indicates the following properties that an ESL methodology should have text/html 2011-11-01T13:39:14-04:00 http://www.edaindia.com/wiki/low_power_asic_design?rev=1320169154&do=diff incomplete Low Power ASICS can be built using a mix of various techniques. These techniques are applicable at various design stages.img * Power Efficient Architecture * Clock Gating * Power Gating * Frequency Scaling * Voltage Scaling * Transistor threshold * Back Biasing * Reduce Oxide Thickness * FINFET * Power efficient circuits * Parallelism in micro-architecture text/html 2011-03-28T13:17:39-04:00 http://www.edaindia.com/wiki/multiclock_designs?rev=1301332659&do=diff incomplete Metastability in digital electronic system is a set of conditions which make it impossible to predict the state of a state element. These conditions commonly occur when the state change is triggered simultaneously with a change in the input conditions which result in a change of the state value. In digital circuits state changes are typically triggered by a 0->1(1->0 in case of neg-edged flops) transition of the clock signal. In order to ensure that the device state elements are alwa… text/html 2009-10-13T13:15:55-04:00 http://www.edaindia.com/wiki/requirement_gathering?rev=1255454155&do=diff Requirement gathering is the first phase of any system design. For the overall product this is done by the sales and marketing team. The team will have multiple meetings with the customer to understand the product needs. Depending on whether the end product is a custom ASIC for a single customer or a catalog product to be used across the industry the kind of work to be done by the sales team varies. For a catalog product the team would have to meet with various customers across the industry unde… text/html 2012-03-17T13:15:18-04:00 http://www.edaindia.com/wiki/start?rev=1332004518&do=diff You are invited to contribute to this knowledgebase on design. Feel free to edit existing pages or add new ones on Aspects of IC Design be it ASIC FPGA or Systems This Wiki has been setup to consolidate the knowledge on System Architecture ASIC Design and Digital Design Techniques. We will be covering Traditional HDL's like Verilog, VHDL and ESL Tools based on C, C++, System Verilog We will cover different modeling strategies using SystemC, SpreadSheets, NS2, OmnetPP etc. And finally we wil… text/html 2010-04-06T10:12:01-04:00 http://www.edaindia.com/wiki/system_architecture?rev=1270563121&do=diff A final product in the hand of the user is a cross domain team work your have the product design team the UI team the Device Driver Team the Application software team the Hardware team the firmware team and the board design team. Each of these teams will have its own architect who will more or less deal with his own area of specialization. For e.g. the hardware architect will be defining the hardware aspect of the system and the software architect will be defining the software aspect of the syst… text/html 2011-05-26T12:20:35-04:00 http://www.edaindia.com/wiki/two_flop_synchronizer?rev=1306426835&do=diff Description This is the basic building block for other Synchronizers. This is made of two flops back to back. The first flop is hand instantiated to ensure that it is a metastability hardened flop. The second flop is an ordinary flop. Both the flops are clocked and reset by the destination domain clock and reset.