Metastability in digital electronic system is a set of conditions which make it impossible to predict the state of a state element. These conditions commonly occur when the state change is triggered simultaneously with a change in the input conditions which result in a change of the state value. In digital circuits state changes are typically triggered by a 0→1(1→0 in case of neg-edged flops) transition of the clock signal. In order to ensure that the device state elements are always predictable one of the constraints imposed in digital design is to ensure that the data remains stable during clock transition. The duration for which the data needs to be stable is denoted by the setup and hold time. Typically for two flops clocked by the same clock the following issues influence the data stability requirement.

1. Clock Pin to Clock Pin skew.
2. Clock to Q delay of the source flop.
3. MAX Path delay from the source pin to the destination pin. This is a combination of
   1. Logic delay.
   2. Net delay.

For circuits operating in a single clock domain, tools are available which will measure the above parameters for each path in the design and ensure that we meet our stability requirements.

For Circuits operating in multiple clock domains where the clocks are derived from the same clock source it is still possible to compute the above factors and ensure that the circuit meets the stability requirements.

For circuits operating in multiple clock domains where more than one clock are sourced from a different clock source a new variable is added to the equation. This variable is the process variation between the two clock sources. e.g. If the requirement is for 30Mhz Clock two different clock generators may generate clocks of 30.0001 and 29.9999 respectively. This difference of 0.0002 MHz can cause periods where communication between the two domains can cause instability.

Multiple parts of a system could be clocked at different frequencies. These clocks could arise from the same clock source or different clock source. e.g. we may have a system consisting of multiple devices communicating with each other using the PCI Interface. These system components will have other internal logic elements which are clocked by a different clock while the part of the logic which connects to the PCI bus will be clocked by the PCI clock. Now since the internal logic and the PCI system are clocked by different clocks it is not possible to signal transition in one domain will be correctly captured in the other. Note: Even in systems where the internal clock generator is tuned to 33 Mhz the two clock domains are to be treated as completely asynchronous. This is because even though we say that the two clock's are running at 33 Mhz process variations are bound to result in a slight deviation in the actual running frequencies of the two clock sources. e.g. one might be running at 33.0001 while the other will be running at 32.9999. This difference of 0.0002Mhz will result in periodic regions where data launched with respect to one domain will violate the setup/hold constraints of the other.

In this case the only requirement is to ensure that the data remains stable for the duration required to ensure that the data is captured by the other domain. Metastability issues are not a factor here.

Notes for this page on Multiclock design

Clock domain clocked by different PLL's should be treated as asynchronous clock domains even through they might be running at the same frequency. This is because the PLL's may have different Jitter, PPM variation and frequency drift characteristics.

The following are the types of synchronization schemes typically used

• Single flop Synchronizer
• Two flop Synchronizer
• Three flop Synchronizer
• Word Synchronizer
• FIFO Synchronizer
• Memory based synchronizer
• FSM Based Synchronizer
• Synchronizers for known clock relationship ( Slow to Fast Synchronizer & fast to slow synchronizer )
• Synchronizers for unknown clock relationship