This is the basic building block for other Synchronizers. This is made of two flops back to back. The first flop is hand instantiated to ensure that it is a metastability hardened flop. The second flop is an ordinary flop. Both the flops are clocked and reset by the destination domain clock and reset.

This syncronization scheme forms the building block for other synchronizers. This synchronizer is used to synchronize single bit control signals from one domain to another.

Input to D1 is clocked in the source clock domain. Due to this, Transition @D1 can occur near the clock edge leading to violation of its setup/hold requirements. This violation will drive the flop to metastable condition. The flop will recover from metastability and Settle to a value of either 0 or 1. If it settles to a correct value then at second clock edge the value at Q1 is available to D2 and after the clock edge @Q2. hence a change in input propagates to the output in 2 clock cycle. On the other hand if Q1 settles to an incorrect value. on the first clock edge, Then D1 will latch the correct data at the second clock edge. Q1 will get this value after the second clock edge. Q2 will get this value after the third clock edge. In this case a change in input will require 3 clock edges to propagate to the output.